1. Field of the Invention
The invention relates to a circuit arrangement for generating the clock of an analog-to-digital converter which operates with interleaved timing, such an analog-to-digital converter and methods for operating the circuit arrangement.
2. Description of the Prior Art
A/D converters are primarily used in digital signal processing. Applications for digital signal processing are, for example, computer-based applications, for example in a microprocessor, or telecommunications applications, for example broadband applications or mobile radio applications. In particular in these applications there is the need for a high-bit-rate analog-to-digital conversion with a very high sampling rate and a correspondingly high level of precision of conversion. In particular for applications in which a very high-bit-rate conversion is necessary, what are referred to as A/D converters which operate with interleaved timing, which are frequently also referred to as converter array or time-interleaved A/D converters (TIADC), are frequently used. This type of A/D converter is referred to below for short as A/D converter.
For the general background of A/D converters which operate with interleaved timing in general and the clock-generating device and track-and-hold circuits thereof in particular, reference is made to U.S. Pat. No. 6,259,281 B1, European patent 1 044 505 B1, European patent 1 006 525 B1, published international patent application 2004/079917 A1 and the article in the conference volume ESSCIRC 2004 by Simon M. Louwsma et al., “A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS”, pages 343-346.
An A/D converter which operates with interleaved timing is configured to convert an analog input signal into a digital output signal. For this purpose, the A/D converter has at least two individual A/D converters which are arranged in parallel with one another. These so-called individual A/D converters operate with interleaved timing and use a track-and-hold circuit which is assigned to this individual A/D converter to sample the analog input signal with interleaved timing. To do this, the track-and-hold circuits are each driven with an individual clock signal. A respective individual clock signal defines a time window within which the respective track-and-hold circuit is activated, that is to say switched on, and thus samples the analog input signal. In the simplest case, these individual clock signals are derived from a common clock signal and are modified in such a way that the respective time windows of the individual clock signals are formed with interleaved timing in their respective time sequence (timing). These individual clock signals with interleaved timing will be referred to as individual clock signals or switch-on signals below.
Precise timing and thus the generation of the individual clock signals are elementary in particular for high-speed applications since this essentially characterizes the speed and thus the efficiency of the entire A/D converter. Particular attention is paid to the fact that the individual clock signals have edges which are as steep as possible in order to permit the respective track-and-hold circuit which is currently being driven by means of such an individual clock signal to sample a sufficiently wide time window and make it possible to drive the analog input signal.
In the genus-forming U.S. Pat. No. 6,259,281 B1 which is mentioned at the beginning, this is achieved by a clock signal generator which is specially provided for this, said clock signal generator having the purpose of generating sub-sampling signals with a relatively high clock edge speed and correctly timed clock edges. The clock signal generator which is known from U.S. Pat. No. 6,259,281 B1 and the corresponding timing of the individual clock signals are briefly described below with reference to FIGS. 1a and 1b. 
The clock signal generator which is designated by the reference 1 has a clock input 2 for inputting a common clock signal CLK and a clock output 3 at which individual clock signals CLK″ which have interleaved timing with respect to one another can be tapped. A window device 4 which is configured to generate a plurality of individual clock signals CLK′ with interleaved timing with respect to one another from the common clock signal CLK (master clock), only one of said individual clock signals CLK′ being shown in FIGS. 1a and 1b, is provided between clock input 2 and clock output 3 for generating the individual clock signals CLK″. The window device 4 has a plurality of AND gates (only one of which is illustrated in FIG. 1a) connected downstream of it, to each of which one of the clock signals CLK′ with interleaved timing and the common clock signal CLK are fed. The individual clock signals CLK″ which have interleaved timing with respect to one another are generated by AND logic operations performed on these two clock signals CLK, CLK′. The individual clock signals CLK″ which are generated in this way therefore simulate the common clock signal CLK, that is to say the period within which a respective individual clock signal CLK″ has a high logic level corresponds to the period T=t2−t1 of a half-clock of the common clock signal CLK.
In this context there is the particular problem that a respective individual A/D converter is intended to perform the A/D conversion as precisely as possible, in particular on one LSB (=least significant bit) in a precise way. For this purpose, the analog input signal in the track-and-hold circuit is firstly loaded (tracked) into memory elements which are embodied, for example, as capacitors, which requires a time period corresponding to the capacitance of the storage capacitors. In particular at very high frequencies and when there is a time window with the duration T of, for example, half a clock of the common clock signal, as in U.S. Pat. No. 6,259,281 B1, there is thus a very short time period available within which the respective analog input signal has to be read into the memory elements and fed via the driver to the individual A/D converter which is respectively connected downstream. However, since the most unfavorable case (worst case) must always be taken into account, that is to say that the analog input signal to be converted requires the entire voltage excursion and as a result all the memory elements of the track-and-hold circuit have to be loaded, the available time window is frequently not sufficient for an A/D converter which is configured for high-speed application. This leads overall to a reduction in the speed of the A/D conversion and thus in the efficiency of the A/D converter. In order nevertheless to ensure a high level of efficiency and thus a high speed of the A/D conversion, the track-and-hold circuit would have to be activated as quickly as possible after the switching-on process in order to load all the memory elements within the time window, but this makes very large demands on the corresponding track-and-hold circuit in terms of circuit technology.
A further problem arises when a defined switch-on edge, with which the track-and-hold circuit is to be switched on, is generated. The switching-off edge of the individual clock signal, at which therefore the track-and-hold circuit is switched off, can typically be set in a relatively precise way. However, generating a defined switch-on edge—with which the track-and-hold circuit is to be switched on—which can fluctuate to a greater or lesser degree is problematic. An undefined, fluctuating switch-on edge can be responsible for the time window for switching on the track-and-hold circuit not being defined and varying over a relatively large range. This is a state which is not desirable in particular for high-frequency applications in which very short time windows are available.